Many high-speed applications such as, for example, microprocessors, use circuit devices that require mutually exclusive signals. For example, decoded multiplexers are commonly used in high-speed microprocessors and, as is well known in the art of microprocessor design, require mutually exclusive select signals. In normal functional operation, only one of the mutually exclusive signals in such a circuit is asserted at any given time, with the rest of the mutually exclusive signals being deasserted. By enabling only one mutually exclusive signal at a time, the circuit device avoids high current conditions in the circuit device. These high current conditions can damage or "burnout" the circuit device as well as result in the circuit device outputting an undefined signal.
FIG. 1 is a block diagram illustrating a small part of a circuit 100 including a conventional decoded multiplexer 101 that is adapted for scan design testing. In particular, the multiplexer 101 has a first select lead 103 connected to receive a select signal s0. The multiplexer 101 also includes a second select lead 105 connected to receive a select signal s. Because the multiplexer 101 is decoded, the select signals s0 and s1 must be mutually exclusive to prevent damage to the multiplexer 101. In this example, the select signals s0 and s1 are provided through scan flip-flops (FF) 107.sub.N and 107.sub.N-1, that form part of a conventional scan chain 107. In a scan mode, the scan chain 107 can be serially loaded with test patterns to test the circuit 100 using well known scan design techniques. The test patterns are typically generated using an automatic test pattern generation (ATPG) software tool, which are well known in the art of test circuits. In particular, each of the flip-flops forming the scan chain 107 has a scan-in (si) lead connected to a scan-out (so) lead of the preceding flip-flop in the scan chain 107. In effect, the scan chain 107 resembles a large shift register. It will be appreciated that scan enable (se), clock and data lines interconnect the flip-flops 107 with other logic circuitry (not shown) of the circuit 100, which are omitted for clarity.
The circuit 100 is tested using scan design techniques well known in the art of test circuits. In a typical scan design scheme, a circuit is tested by: (a) configuring the circuit into a scan mode and "scanning in" a test pattern into the circuit's scan chain; (b) configuring the circuit into a normal functional mode and allowing the test pattern to propagate through the logic circuitry of the circuit; (c) pulsing the circuit and capturing the response in the scan chain; (d) configuring the circuit into the scan mode and "scanning out" the captured data from the scan chain for comparison with the expected values.
During the scan mode as the test pattern is scanned in or applied to the circuit 100, the test pattern may cause the flip-flops 107.sub.N and 107.sub.N-1 to have values that violate the mutual exclusivity requirements of the multiplexer 101 regarding the select signals s0 and s1. The multiplexer 101 may be damaged as described above due to a high current condition caused by this violation of the mutual exclusivity requirement. One conventional solution is to constrain the ATPG software tool used to generate the test patterns to avoid patterns that violate the mutual exclusivity requirement of the multiplexer 101 (and, of course, every other circuit device in the circuit 100 that has a mutual exclusivity requirement). As a result, the complexity, computation time, and cost of the test pattern generation are typically relatively high. In addition, the constraints may result in poor fault coverage of the circuit 100.
Moreover, the response of the circuit 100 to the test patterns captured by the scan chain 107 may also violate the mutual exclusivity requirement of the multiplexer 101 either directly or as the capture data is scanned out of the scan chain 107. Consequently, the ATPG software tool must be further constrained to generate test patterns that cause the circuit 100 to respond with capture data that complies with the mutual exclusivity requirements of the multiplexer 101. Of course, the ATPG software tool is similarly constrained to avoid violating the mutual exclusivity requirements (if any) of every other circuit device in the circuit 100. These two constraints cause a significant increase in the complexity, computation time and cost of test pattern generation, and typically reduce the fault coverage of the test patterns.
FIG. 2 shows a block diagram of a portion of a circuit 200 implementing a typical conventional solution to the above problem. The circuit 200 is substantially similar to the circuit 100 (FIG. 1) except that the circuit 200 includes a gating circuit 201 coupling the flip-flops 107.sub.N and 107.sub.N-1 to the multiplexer 101. The circuit 200 has a similar gating circuit for each circuit device requiring mutually exclusive signals.
More specifically, in this conventional solution the select leads 103 and 105 of the multiplexer 101 are connected to the gating circuit 201 rather than directly to the flip-flops 107.sub.N and 107.sub.-1. The gating circuit 201 is also connected to receive a signal rst.sub.-- tri.sub.-- en via a line 203. The rst.sub.-- tri.sub.-- en signal is a "global" signal (i.e., a signal provided to the gating circuits of all of the circuit devices with mutual exclusivity requirements) typically provided by a conventional Reset block or test access port (TAP) controller. In particular, TAP controllers are defined in "The IEEE Standard Test Access Port and Boundary Scan Architecture, IEEE Standard 1149.1-1990", which is incorporated herein by reference. Such TAP controllers and Reset blocks are well known in the art of test circuits.
The gating circuit 201 functions to gate the signals from the flip-flops 107.sub.N and 107.sub.N-1 to the select leads 103 and 105 of the multiplexer 101 only during the normal operation mode. The gating circuit 201 operates to force the signals on the select leads 103 and 105 to predetermined mutually exclusive logic levels. Thus, while test patterns are being scanned into the scan chain 107, the gating circuit 201 prevents the test pattern from propagating to the multiplexer 101. Accordingly, the test pattern need not be constrained to comply with the mutual exclusivity requirements of the select signals s0 and s1 during the scan in phase. Although the test pattern, when finally scanned in, does have to meet the mutual exclusivity requirements of the select signals s0 and s1. In addition, as described below in conjunction with FIGS. 3 and 4, the gating circuit 201 does not address the response constraint.
FIG. 3 is a circuit diagram of a conventional gating circuit 201. In this example, the gating circuit 201 includes a two-input OR-gate 301 and a two-input AND-gate 303. The OR-gate 301 has an inverting input lead connected to receive the rst.sub.-- tri.sub.-- en signal. The other input lead of the OR-gate 301 is connected to the output lead 305 of the flip-flop 107.sub.N. The AND-gate 303 has one input lead connected to receive the rst.sub.-- tri.sub.-- en signal while its other input lead is connected to the output lead 307 of the flip-flop 107.sub.N-1. The rst.sub.-- tri.sub.-- en signal is generated to have a logic high level during the normal functional mode and to have a logic low level during the scan mode.
When the rst.sub.-- tri.sub.-- en signal is at a logic low level, the inverting input lead of the OR-gate 301 forces the OR-gate 301 to output the select signal s1 at a logic high level onto the select lead 105. The logic low level of the rst.sub.-- tri.sub.-- en signal also forces the AND-gate 303 to output the select signal s0 at a logic low level onto the select lead 103. The gating circuit 201, by forcing the select signals s0 and si to respectively have logic low and logic high levels, ensures that the select signals are mutually exclusive during the scan mode.
Conversely, when the rst.sub.-- tri.sub.-- en signal is at a logic high level, the inverting input lead of the OR-gate 301 allows the OR-gate 301 to output onto the select lead 105 the signal s1 with a logic level equivalent to the stored logic level of the flip-flop 107.sub.N received through the lead 305. The logic high level of the rst.sub.-- tri.sub.-- en signal also allows the AND-gate 303 to output onto the select lead 103 the signal s0 with a logic level equivalent to the stored logic level of the flip-flop 107.sub.N-1 received through the lead 307. Accordingly, the gating circuit 201, in effect, isolates the flip-flops 107.sub.N and 107.sub.N-1 from the multiplexer 101 (FIG. 2) during the scan mode and propagates the stored signals in the flip-flops to the multiplexer 101 during the normal mode.
In particular, the flip-flops in the scan chain 107 (FIG. 2) receive the clock signal CK illustrated in the timing diagram of FIG. 4. In the first portion of the timing diagram, the circuit 200 is configured to scan in the test pattern. More specifically, the circuit 200 is configured in the scan mode as indicated by the scan enable signal se being asserted (i.e., at a logic high level) and the rst.sub.-- tri.sub.-- en signal being deasserted (i.e., at a logic low level).
After the test pattern is scanned in, the circuit 200 is configured into the normal mode and the next clock cycle is used to load the response data into the scan chain 107. More specifically, just prior to the rising edge of the capture pulse CP, the scan enable signal se is deasserted and the rst.sub.-- tri.sub.-- en signal is asserted, configuring the scan chain 107 into the normal mode. In the normal mode, the circuit 200 operates on the test pattern stored in the scan chain, including the pattern stored in the flip-flops 107.sub.N and 107.sub.N-1 and propagated to the logic circuitry through the gating circuit 201.
For example, as shown in FIG. 5, the test pattern loaded in the scan chain 107, can include flip-flops 107.sub.M and 107.sub.M+1 that cause logic circuitry 501 to generate logic signals that are received by the flip-flops 107.sub.N and 107.sub.N-1. Then the leading edge of the capture pulse CP (FIG. 4) causes the flip-flops 107.sub.N and 107.sub.N-1 to store the logic levels of these received signals, that are then provided to the gating circuit 201. However, because the capture pulse CP is a "normal" mode operation, the gating circuit 201 will allow the response or capture data from the flip-flops 107.sub.N and 107.sub.N-1 to propagate to the multiplexer 101 throughout the remaining duration of the capture pulse. Thus, if the response data captured in the flip-flops 107.sub.N and 107.sub.N-1 have identical logic levels (e.g., the zeros indicated in FIG. 5), the gating circuit 201 propagates non-mutually exclusive select signals to the multiplexer 101, which can damage the multiplexer 101 as described above. Consequently, in this conventional scheme, the ATPG software tool must still be constrained to avoid generating test patterns causing the circuit 200 (FIG. 2) from generating response or capture data that provide non-mutually exclusive select signals to the multiplexer 101 (and any other circuit device in the circuit 200 that requires mutually exclusive signals). Accordingly, there is a need for a circuit that avoids the "response data constraint" on the ATPG tool in generating test patterns.